1. Field of the Invention
The present invention relates in general to a semiconductor manufacturing technique, and more particularly, to a method for manufacturing a semiconductor wafer.
2. Description of the Related Art
Semiconductor package structures may include semiconductor packages implementing conductive bumps. Such semiconductor packages may include, for example, flip chip packages and wafer level packages. Semiconductor packages implementing conductive bumps may be advantageous in electrical and thermal characteristics and mounting area, as compared to wire bonding packages.
Conductive bumps may be provided on semiconductor chips at a wafer level. FIG. 1 is a schematic cross-sectional view of a conventional semiconductor wafer 10 having conductive bumps 16.
Referring to FIG. 1, the semiconductor wafer 10 may have an active surface 11 and a back surface 12. A plurality of integrated circuits 13 may be provided on and/or in the semiconductor wafer 10. Scribe lines 14 may be provided between adjacent integrated circuits 13. I/O pads 15 may be provided on the active surface 11 of the semiconductor wafer 10. Conductive bumps 16 may be provided on the I/O pads 15. The conductive bumps 16 may be fabricated from a conductive material, for example a solder and/or gold (Au). The conductive bumps 16 may serve as external connection terminals to be mechanically and electrically connected to external devices.
The semiconductor wafer 10 may be separated into individual semiconductor chips. The separation process may be achieved via a mechanical sawing technique, for example. Before the sawing process, a portion of a back surface of the semiconductor wafer 10 may be removed. Such a process may be referred to as a backgrinding process and/or a backlapping process. The backlapping process may reduce the thickness of a semiconductor wafer 10. For example, a semiconductor wafer having a diameter of 8 inches may have an initial thickness between 730 μm and 750 μm. A semiconductor wafer having a diameter of 12 inches may have an initial thickness between 780 μm and 800 μm. After a backlapping process, the thickness of semiconductor wafers may be 500 μm or less.
Although conventional fabricating techniques are generally thought to be acceptable, they are not without shortcomings. For example, a backlapping process may cause bending and/or warpage of the semiconductor wafer. If a backlapping process is performed on a semiconductor wafer having conductive bumps, the conductive bumps and/or the semiconductor wafer may be damaged, and/or the conductive bumps may be separated from the semiconductor wafer.
The bending and/or warpage of a semiconductor wafer may result from heat generated during a backlapping process. For example, the coefficient of thermal expansion (CTE) of a main material of the integrated circuits may be different from that of a main material of the wafer, for example silicon. Therefore, the active surface of the semiconductor wafer having the integrated circuits may have a different CTE as compared to that of the back surface of the semiconductor wafer. Such a difference in CTE may create critical faults in the semiconductor wafer, especially one that may have a reduced thickness after a backlapping process.
FIG. 2 is a photograph showing warpage of a semiconductor wafer after a backlapping process.